On November 10, AMD will formally introduce its fourth-generation EPYC CPUs, code-named Genoa. There will be three families in the AMD Zen 4 lineup: the regular Zen 4 for EPYC Genoa, the compute density-optimized Zen 4C for EPYC Bergamo, and the cache-optimized Zen 4 V-Cache for the EPYC Genoa-X series.
Additionally, the portfolio will include an affordable entry-level server option called EPYC Siena that will have the same Zen 4 cores as SP5, but on a brand-new platform called SP6 that will again place a greater emphasis on TCO optimization. The EPYC 8004 family will serve as the brand name for the lineup.
Up to 12 CCDs, 96 cores, and 192 threads are included in the standard Zen 4 lineup. 32 MB of L3 cache and 1 MB of L2 cache are provided with each CCD. The AVX-512 (256b data route), BFLOAT16, VNNU, addressable memory of 57b/52b, and an improved IOD with an internal AMD Gen3 Infinity Fabric architecture with increased bandwidth will all be included in the EPYC 9004 CPUs (die-to-die interconnect).
The AMD platform will offer options for 2, 4, 6, 8, 10, and 12 interleavings, as well as 12 DDR5 channels with up to 4800 Mbps DIMM support.
With 2 DIMMs per channel and a maximum of 6 TB/capacity per socket, both RDIMM and 3DS RDIMM will be supported (using 256 GB 3DS RDIMMs). There will be 64 IO lanes supporting CXL 1.1+ with bifurcations down to x4 and SDCI, 32 SATA lanes, 12 PCIe Gen 3 lanes, and 160 gen 5 lanes are accessible on the 2P platform (Smart Data Cache Injection).
The EPYC 9000 “Genoa” CPU range from AMD will significantly improve performance for servers. A 192-core and 384-thread dual-socket setup would undoubtedly break several world records since we have already seen a partial 128-core/256-thread configuration defeat all current-gen server CPUs. By the end of the year, AMD’s EPYC 9000 Genoa CPU line is anticipated to be available in servers, considerably ahead of Intel’s Sapphire Rapids-SP Xeon line, which is now scheduled to launch in early 2023.
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