Imec showcases its 2036 Roadmap for Sub-1nm Process and Transistors

    At its Future Summit event in Antwerp, Belgium, Imec, the world’s most advanced semiconductor research organization, recently presented its sub-‘1nm’ silicon and transistor roadmap. The roadmap provides a general schedule for the next major process nodes and transistor architectures that the business will research and develop in its labs in collaboration with industry giants like TSMC, Intel, Samsung, and ASML, among others, through 2036.


    The roadmap includes breakthrough transistor designs that progress from standard FinFET transistors that will last until 3nm to new Gate All Around (GAA) nanosheets and worksheet designs at 2nm and A7 (seven angstroms), respectively, and breakthrough designs such as CFETs and atomic channels at A5 and A2. Because ten Angstroms equals one nanometer, Imec’s roadmap includes sub-‘1nm’ process nodes.

    Consider imec to be a sort of silicon Switzerland. While the semiconductor research organization imec isn’t well-known, it serves as the industry’s quiet cornerstone, bringing fierce competitors like Intel, TSMC, and Samsung together with chip toolmakers like ASML and Applied Materials, as well as equally important semiconductor software design companies (EDA) like Cadence and Synopsys, in a non-competitive environment. The corporations will collaborate to define the next generation of tools and software they will employ to build and manufacture the chips that power the planet.


    In the face of the significantly rising complexity and cost of designing chips and the equipment that creates them, a consistent approach is becoming increasingly vital. I also collaborate with companies such as Intel and TSMC for R&D on innovative technologies that can be used in their latest processors. In collaboration with its long-time partner ASML, the business is also known for helping to pioneer EUV technology.

    At the end of the day, all the cutting-edge chipmakers rely on a small number of crucial toolmakers for much of their equipment, thus some amount of standardization is required. However, this necessitates R&D activities that can begin a decade before deployment, implying that imec’s roadmaps can provide a considerably broader view of impending semiconductor breakthroughs than AMD, Intel, and Nvidia’s near-term product roadmaps. Many of those items would not have been conceivable without imec’s collaborative work, which began years ago.


    As nodes advance, costs rise, and demand for additional processing power, particularly for machine learning, grows non-linearly, the industry faces increasing hurdles.

    Imec has high hopes in Moore’s Law

    Imec is certain that Moore’s Law is still valid 52 years later, albeit we don’t believe this holds for the economic component of the law, which stipulated a reduced cost per transistor over time. Chip design prices are soaring as a result of more complex design guidelines and longer design cycle durations, resulting in higher cost-per-transistor. Furthermore, single-threaded performance gains have slowed from the heady days of 50% annual gains in the late 1990s and early 2000s to 5% each year.


    While the demand for greater computes power used to double every two years, roughly following the performance advancements provided by Moore’s Law, the raw compute power required for machine learning/AI doubles every six months, according to Imec. This is a difficult problem because even doubling the number of transistors won’t be enough to stay up. Imec believes that a three-pronged approach of dimensional scaling (including improved density and packaging technologies), novel materials and device architectures, and system technology co-optimization (SCTO) will keep the industry on pace.

    The first step is to make the next-generation tools available. Due to the 0.33 aperture of today’s 4th-Gen EUV lithography machines, chipmakers will have to adopt multi-patterning techniques (more than one exposure per layer) to create the tiniest of features at 2nm and beyond. There’s a higher probability of defects because the wafer will have to be ‘printed’ twice for a single layer. Reduced yields and longer cycle (production) times will ensue, adding to higher costs.


    The aperture of the next-generation High-NA models (5th-Gen) will be 0.55. This increased precision will allow even smaller structures to be created in a single exposure, decreasing design complexity and enhancing yields, cycle times (200+ wafers per hour), and cost. Imec and ASML estimate that these tools will be ready for mass production in 2026. In the first half of 2023, ASML will complete the first $400 million High NA tool. Imec will work out of the ASML test lab to provide chipmakers faster access to the machine, which is a first (ASML generally transports the tool to imec’s fab).

    GAA/nanosheet and worksheet transistors (basically a denser variant of GAA) are expected to last to the A7 node, according to Imec. When complementary FET (CFET) transistors come around 2032, they will reduce the footprint, even more, enabling more densely packed standard cell libraries. We’ll eventually see CFETs with atomic channels, which will boost performance and scalability even further.


    Improved Back End of Line (BEOL) techniques will be required to increase transistor density and performance characteristics even further. The BEOL steps are concerned with connecting the transistors to enable communication (signals) and power delivery.

    These secondary density-improving strategies are known as scaling boosters’ by Imec because they contribute to higher transistor density and performance despite not being directly tied to transistor size or placement

    Direct metal etches techniques for interconnects, as well as self-aligned vias with air gaps, are on the roadmap for future enhancements. The small cables that enable power delivery and communication have become one of the most significant scaling obstacles. This issue will only get worse as time goes on, as these wires will only need to be a few atoms thick. Imec is also looking at new metals to replace copper, with graphene being one of the contenders.


    When we look beyond 2030, we can see that imec believes that new materials will replace silicon and that 2D atomic channels will develop. Magnetics-based gates, according to Imec, could emerge as an alternative as the industry pushes inexorably towards quantum computing.

    also read:

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